When HCL Technologies Limited was announced as a Design Solution Partner in Samsung’s Advanced Foundry Ecosystem on March 27, 2025, the semiconductor world took notice. The news broke from Noida, India, at 6:27 am EDT, with Taejoong Song, Vice President and head of the Technology Planning 2 Team at Samsung Electronics, highlighting the strategic importance of the tie‑up. Sanjay Gupta, Corporate Vice President of North Asia at HCLTech, echoed the sentiment, emphasizing the rapid growth of the semiconductor sector. The partnership, part of the SAFE™‑DSP program, promises to blend HCLTech’s 200,000‑strong engineering workforce with Samsung’s 5nm, 4nm and soon‑to‑arrive 3nm process technologies, accelerating innovation for customers worldwide.
Background: Samsung’s Advanced Foundry Ecosystem
Since its launch in 2019, the Samsung Advanced Foundry Ecosystem (SAFE™) has acted as a bridge between chip designers and Samsung’s manufacturing might. The ecosystem offers a suite of programs – from Virtual Design Partner (VDP) to Design Solution Partner (DSP) – each adding layers of support, IP sharing, and access to cutting‑edge process nodes. Historically, SAFE™ has helped more than 150 design houses prototype on Samsung’s 7nm and 5nm platforms, cutting time‑to‑market by an average of 30 percent. The ecosystem’s latest evolution, the SAFE™‑DSP track, is geared toward companies that can deliver end‑to‑end ASIC services, meaning they not only design but also integrate, test and ship silicon.
What the SAFE™‑DSP Partnership Means
Under the new agreement, HCLTech will act as a one‑stop shop for ASIC customers seeking Samsung’s advanced process technologies. The core offerings include:
- Full‑stack ASIC design services, from spec‑to‑tape‑out.
- Access to Multi‑Project Wafer (MPW) programmes, which let several customers share wafer space – a model that can shave up to 70 % off prototyping costs.
- Dedicated technical support from Samsung’s process engineers, including on‑site training for HCLTech staff.
- Turnkey project management that aligns design milestones with Samsung’s fab schedules.
The agreement also bundles a “spec‑to‑platform” methodology that HCLTech has honed over the past decade, allowing rapid migration of system‑on‑chip (SoC) designs into Samsung’s 5nm, 4nm and future 3nm nodes. For customers in telecom, automotive and consumer electronics, that could translate into months saved and billions of rupees preserved.
Voices from the Front Line
“HCLTech’s presence in India, coupled with its global expertise and capabilities in SoC platforms and IP partnerships, plays a key role in advancing next‑generation silicon solutions,” said Taejoong Song. “The partnership underscores our shared commitment to innovation and excellence, accelerating the time‑to‑market for new silicon technologies.”
“The semiconductor industry is experiencing significant growth, and our partnership with Samsung Foundry highlights our dedication to developing state‑of‑the‑art custom silicon,” added Sanjay Gupta. “By leveraging the strengths of both HCLTech and Samsung Foundry, we aim to drive advancements that meet the changing demands of the global market.”
Analyst Priya Menon of TechInsights notes, “This move puts HCLTech in the same league as established ASIC houses like Arm and Synopsys, but with the advantage of direct fab access. Expect a ripple effect across Indian design services firms.”
Industry Impact and Expert Views
Industry data points illustrate the partnership’s scale. In Q1 2025, global ASIC spend rose 12 % year‑over‑year, reaching $18 billion, according to SEMI. Samsung’s foundry revenue, buoyed by its 5nm production, hit $10.3 billion in 2024, a 9 % increase from the prior year. By plugging HCLTech’s 200,000 engineers across 52 countries into Samsung’s cutting‑edge nodes, the duo can potentially capture a sizable slice of the projected $25 billion AI‑driven chip market slated for 2027.
Cost‑saving estimates from the MPW model suggest that a typical 5nm prototype that once cost $1.5 million could now be delivered for as low as $450,000 – a figure that aligns with the “up to 70 % reduction” cited in industry benchmarks. Moreover, HCLTech’s stock on the Bombay Stock Exchange settled at 1,626.80 ₹ on March 26, 2025, just before the announcement, hinting at market optimism.
Upcoming SAFE™ Forum 2025 and Next Steps
The partnership will be showcased at the SAFE™ Forum 2025, a two‑city event designed to cement collaborations across the ecosystem. The first leg runs on June 3, 2025 in San Jose, California, with the second scheduled for July (exact date pending) in Seoul, South Korea. The forum’s theme – “Alliance for Smarter Silicon” – will feature plenary sessions on GenAI‑powered chip innovation, partner pavilions, and hands‑on labs where HCLTech plans to demo its spec‑to‑platform flow on Samsung’s 3nm trial wafers.
Looking ahead, both firms have outlined a roadmap that includes joint R&D labs in India and Korea, co‑development of AI‑optimized compute blocks, and a target to roll out three new custom ASIC families by the end of 2026.
Historical Perspective: From Virtual Design Partner to Design Solution Partner
HCLTech’s journey with Samsung began in December 2024 when the company joined the Virtual Design Partner (VDP) program. The VDP initiative was Samsung’s first attempt to merge remote design expertise with its fab capabilities, allowing partners to simulate process layers before silicon was even etched.
Success in the VDP arena – demonstrated by a 40 % faster design‑cycle for a telecom client – paved the way for the more expansive DSP role. In the DSP model, HCLTech moves beyond virtual simulations to actual tape‑out and volume production, marking a significant upgrade in responsibility and revenue potential.
Experts argue this progression mirrors a broader industry trend: design houses are no longer just “design‑only” outfits; they are evolving into full‑stack solution providers that can shepherd a chip from concept to market.
Frequently Asked Questions
How will this partnership affect Indian semiconductor design firms?
The HCLTech‑Samsung tie‑up gives Indian designers direct access to world‑class 5nm‑3nm process technologies and MPW cost‑saving programmes. Smaller firms that partner with HCLTech can now prototype at a fraction of previous costs, potentially unlocking new business in telecom and automotive sectors.
What specific services will HCLTech provide under the DSP program?
HCLTech will offer end‑to‑end ASIC design, verification, tape‑out, and post‑silicon support using Samsung’s advanced nodes. It will also manage MPW projects, provide training on Samsung’s process nuances, and coordinate turnkey production schedules.
Why is the Multi‑Project Wafer (MPW) model important for customers?
MPW lets several customers share a single wafer, dramatically cutting prototyping expenses—industry benchmarks show up to 70 % savings. It also speeds up time‑to‑first‑silicon, as designers can tap into Samsung’s fab slots that would otherwise be reserved for larger volume runs.
When and where will the SAFE™ Forum 2025 take place?
The first leg is scheduled for June 3, 2025 in San Jose, California, with a second session slated for July 2025 in Seoul, South Korea. Both events will showcase the latest in AI‑driven chip design and feature demos from HCLTech and other ecosystem partners.
What does this partnership mean for Samsung’s foundry business?
By onboarding a heavyweight design services firm like HCLTech, Samsung broadens its customer base beyond traditional fab‑only clients. The added design‑to‑manufacturing pipeline helps fill wafer capacity, especially for emerging AI and automotive chips, bolstering its revenue outlook through 2027.
